530 lines
20 KiB
Python
530 lines
20 KiB
Python
import re
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from abc import abstractmethod
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import numpy
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# from concho import dell
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import math
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class Item():
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def __init__(self, uid):
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self.uid = uid
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class Chassis(Item):
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def __init__(self, uid):
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super().__init__(uid)
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self.max_num_servers = 1
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self.num_cpu_slots_per_server = 2
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if re.match('dell-poweredge-r9.*', uid):
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self.num_cpu_slots_per_server = 4
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if re.match('dell-poweredge-c6.*', uid):
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self.max_num_servers = 4
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self.num_dimm_slots_per_channel = 2
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class Dimm(Item):
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def __init__(self, num_gb, num_mhz, mem_type):
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uid = "%s-%s-%s" % (mem_type, num_gb, num_mhz)
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super().__init__(uid)
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self.num_gb = num_gb
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self.num_mhz = num_mhz
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self.mem_type = mem_type
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class Cpu(Item):
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def __init__(self, proc_id):
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super().__init__(proc_id)
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cpuTable = numpy.genfromtxt('cpu_table.tsv', dtype=("|U32", float, int, float, float, float), names=True, delimiter='\t')
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for cpu_id, clock, num_cores, max_cpus, tdp, cpumark in zip(cpuTable['id'], cpuTable['clock'], cpuTable['num_cores'], cpuTable['max_cpus'], cpuTable['tdp'], cpuTable['cpumark_1_cpu']):
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# print(cpu_id)
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if cpu_id == proc_id:
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# print('found '+procId)
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break
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assert cpu_id == proc_id, 'Failed to find %s in cputable' % proc_id
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self.clock = clock
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self.num_cores = num_cores
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self.max_cpus = max_cpus
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self.tdp = tdp
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self.cpumark = cpumark
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@property
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def architecture(self):
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proc_id = self.uid
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if re.match('intel-core-i[357]-8[0-9][0-9][0-9][ktbuh]', proc_id):
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return 'coffeelake'
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elif re.match('intel-xeon-silver-[0-9]3[0-9][0-9]', proc_id):
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return 'icelake'
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elif re.match('intel-xeon-gold-[0-9]3[0-9][0-9]', proc_id):
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return 'icelake'
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elif re.match('intel-xeon-platinum-[0-9]3[0-9][0-9]', proc_id):
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return 'icelake'
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elif re.match('intel-xeon-silver-[0-9]2[0-9][0-9]', proc_id):
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return 'cascadelake'
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elif re.match('intel-xeon-gold-[0-9]2[0-9][0-9]', proc_id):
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return 'cascadelake'
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elif re.match('intel-xeon-platinum-[0-9]2[0-9][0-9]', proc_id):
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return 'cascadelake'
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elif re.match('intel-xeon-gold-[0-9]1[0-9][0-9]', proc_id):
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return 'skylake'
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elif re.match('intel-xeon-platinum-[0-9]1[0-9][0-9]', proc_id):
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return 'skylake'
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elif re.match('intel-xeon-e5-26[0-9][0-9][lwa]*v4', proc_id):
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return 'broadwell'
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elif re.match('intel-xeon-e5-26[0-9][0-9][lwa]*v3', proc_id):
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return 'haswell'
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elif re.match('intel-xeon-e5-26[0-9][0-9][lwa]*v2', proc_id):
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return 'ivy bridge'
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elif re.match('intel-xeon-e5-26[0-9][0-9][lwa]*', proc_id):
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return 'sandy bridge'
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elif re.match('intel-xeon-x56[0-9][0-9]', proc_id):
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return 'gulftown'
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elif re.match('intel-xeon-x55[0-9][0-9]', proc_id):
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return 'gainestown'
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elif re.match('intel-xeon-e54[0-9][0-9]', proc_id):
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return 'harpertown'
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elif re.match('intel-xeon-51[0-9][0-9]', proc_id):
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return 'woodcrest'
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elif re.match('amd-epyc-[0-9][0-9fh][0-9]1', proc_id):
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return 'naples'
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elif re.match('amd-epyc-[0-9][0-9fh][0-9]2', proc_id):
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return 'rome'
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elif re.match('amd-epyc-[0-9][0-9fh][0-9f]3', proc_id):
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return 'milan'
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else:
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assert False, 'unhandled processor id : %s' % proc_id
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@property
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def num_dp_flop_per_cycle(self):
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proc_arch = self.architecture
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simd_id = get_simd_id(proc_arch)
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num_simd_per_core = 1
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if proc_arch in ['skylake', 'cascadelake']:
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# from https://en.wikipedia.org/wiki/List_of_Intel_Xeon_microprocessors : Xeon Platinum, Gold 61XX, and Gold 5122 have two AVX-512 FMA units per core; Xeon Gold 51XX (except 5122), Silver, and Bronze have a single AVX-512 FMA unit per core
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if re.match('intel-xeon-gold-5122', self.uid):
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num_simd_per_core = 2
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# https://en.wikichip.org/wiki/intel/xeon_gold/5222 : 'Note that this is the only processor in the Xeon Gold 52xx series with two 512b FMA units.'
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if re.match('intel-xeon-gold-5222', self.uid):
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num_simd_per_core = 2
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if re.match('intel-xeon-gold-61[0-9][0-9]', self.uid):
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num_simd_per_core = 2
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if re.match('intel-xeon-gold-62[0-9][0-9]', self.uid):
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num_simd_per_core = 2
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if re.match('intel-xeon-gold-63[0-9][0-9]', self.uid):
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num_simd_per_core = 2
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# from https://www.microway.com/knowledge-center-articles/detailed-specifications-of-the-amd-epyc-rome-cpus/:
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# - Full support for 256-bit AVX2 instructions with two 256-bit FMA units per CPU core. The previous “Naples” architecture split 256-bit instructions into two separate 128-bit operations
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# - Up to 16 double-precision FLOPS per cycle per core
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# - Double-precision floating point multiplies complete in 3 cycles (down from 4)
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# note : zen2 rome core has 2 256 bits fma units per core, which corresponds to avx2 technology according to https://stackoverflow.com/questions/15655835/flops-per-cycle-for-sandy-bridge-and-haswell-sse2-avx-avx2:
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# Intel Haswell/Broadwell/Skylake/Kaby Lake/Coffee/... (AVX+FMA3):
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# - 16 DP FLOPs/cycle: two 4-wide FMA (fused multiply-add) instructions
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# - 32 SP FLOPs/cycle: two 8-wide FMA (fused multiply-add) instructions
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# - (Using 256-bit vector instructions can reduce max turbo clock speed on some CPUs.)
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# so, rome core have one avx2 simd, which has 2 256-bit fmadd units. Each 256-bit fma unit is able to perform 4*2 = 8 dflops/cycle; and in total we have 16 dflops per cycle per rome core, which is confirmed by internet
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if proc_arch in ['icelake']:
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# https://www.microway.com/knowledge-center-articles/detailed-specifications-of-the-ice-lake-sp-intel-xeon-processor-scalable-family-cpus/
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# > AVX-512 instructions (up to 16 double-precision FLOPS per cycle per AVX-512 FMA unit)
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# > Two AVX-512 FMA units per CPU core (available in all Ice Lake-SP CPU SKUs)
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# https://www.intel.com/content/www/us/en/products/sku/215269/intel-xeon-silver-4314-processor-24m-cache-2-40-ghz/specifications.html shows that even xeon silver 4314 has 2 AVX 512 fma units
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num_simd_per_core = 2
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if proc_arch == 'rome':
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num_simd_per_core = 1
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dp_flops_per_cycle = num_simd_per_core * simd_id_to_dp_flops_per_cycle(simd_id)
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# print(self.uid, dp_flops_per_cycle)
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return dp_flops_per_cycle
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@property
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def num_ram_channels(self):
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return {
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'skylake': 6,
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'coffeelake': 6,
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'cascadelake': 6,
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'icelake': 8,
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'rome': 8,
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'milan': 8
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}[self.architecture]
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def get_proc_architecture(proc_id):
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return Cpu(proc_id).architecture
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def get_proc_arch_transistor_size(proc_id):
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return {
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'woodcrest': 65,
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'harpertown': 45,
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'gainestown': 45,
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'gulftown': 32,
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'sandy bridge': 32,
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'ivy bridge': 22,
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'haswell': 22,
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'broadwell': 14,
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'skylake': 14,
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'coffeelake': 14,
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'cascadelake': 14
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}[get_proc_architecture(proc_id)]
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def simd_id_to_dp_flops_per_cycle(simd_id):
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"""
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:param str simd_id: eg 'avx2'
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"""
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# from https://stackoverflow.com/questions/15655835/flops-per-cycle-for-sandy-bridge-and-haswell-sse2-avx-avx2
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# Intel Core 2 and Nehalem:
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#
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# 4 DP FLOPs/cycle: 2-wide SSE2 addition + 2-wide SSE2 multiplication
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# 8 SP FLOPs/cycle: 4-wide SSE addition + 4-wide SSE multiplication
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#
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# Intel Sandy Bridge/Ivy Bridge:
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#
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# 8 DP FLOPs/cycle: 4-wide AVX addition + 4-wide AVX multiplication
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# 16 SP FLOPs/cycle: 8-wide AVX addition + 8-wide AVX multiplication
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#
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# Intel Haswell/Broadwell/Skylake/Kaby Lake:
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#
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# 16 DP FLOPs/cycle: two 4-wide FMA (fused multiply-add) instructions
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# 32 SP FLOPs/cycle: two 8-wide FMA (fused multiply-add) instructions
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# https://www.dell.com/support/kbdoc/fr-fr/000137696/amd-rome-is-it-for-real-architecture-and-initial-hpc-performance
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# The Rome micro-architecture can retire 16 DP FLOP/cycle, double that of Naples which was 8 FLOPS/cycle
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return {
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'sse4.1': 4,
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'sse4.2': 4,
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'avx': 8,
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'avx2': 16,
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'avx-512': 16,
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}[simd_id]
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def get_simd_id(proc_arch):
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"""
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:param str proc_arch: eg 'broadwell'
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:return str: eg 'sse4'
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"""
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return {
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'woodcrest': 'sse4.1',
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'harpertown': 'sse4.1',
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'gainestown': 'sse4.2',
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'gulftown': 'sse4.2',
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'sandy bridge': 'avx',
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'ivy bridge': 'avx',
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'haswell': 'avx2',
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'broadwell': 'avx2',
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'skylake': 'avx-512',
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'cascadelake': 'avx-512',
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'icelake': 'avx-512',
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'coffeelake': 'avx2',
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# from https://www.microway.com/knowledge-center-articles/detailed-specifications-of-the-amd-epyc-rome-cpus/:
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# - Full support for 256-bit AVX2 instructions with two 256-bit FMA units per CPU core. The previous “Naples” architecture split 256-bit instructions into two separate 128-bit operations
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# - Up to 16 double-precision FLOPS per cycle per core
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# - Double-precision floating point multiplies complete in 3 cycles (down from 4)
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'rome': 'avx2',
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'milan': 'avx2',
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}[proc_arch]
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class MemChannel():
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def __init__(self):
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self.dimms = []
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class CpuSlotMem():
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def __init__(self):
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self.mem_channels = []
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class Config():
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def __init__(self, configurator):
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self.configurator = configurator
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self.num_servers = 0
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self._num_cpu_per_server = 0
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self.cpu = None
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self.cpu_slots_mem = []
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@property
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def chassis(self):
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return self.configurator.chassis.item
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@staticmethod
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def _find_dimm_combination(num_dimm_slots_per_channel, min_ram_per_channel, available_dimms):
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available_dimms.append(Option(Dimm(0, 0, 'dummy'), 0.0)) # fake dimm to represent empty slot
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slot_options = []
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# try all combinations of dimms
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best_slot_options = None
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best_price = None
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for slot_index in range(num_dimm_slots_per_channel):
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slot_options.append(0)
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no_more_configs = False
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while no_more_configs is False:
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config_capacity = 0
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config_price = 0
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for slot_index in range(num_dimm_slots_per_channel):
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dimm_option = available_dimms[slot_options[slot_index]]
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config_capacity += float(dimm_option.item.num_gb) * math.pow(2.0, 30.0)
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config_price += dimm_option.price
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if config_capacity >= min_ram_per_channel: # only remember the combination if it complies with the minimal memory constraint
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if best_price is None or config_price < best_price:
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best_price = config_price
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best_slot_options = slot_options.copy()
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# generate the next combination of dimms
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for slot_index in range(num_dimm_slots_per_channel):
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slot_options[slot_index] += 1
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if slot_options[slot_index] < len(available_dimms):
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break
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else:
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if slot_index == num_dimm_slots_per_channel - 1:
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no_more_configs = True # all combinations of dimm in the slots have been covered
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else:
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slot_options[slot_index] = 0
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assert best_slot_options is not None, "Failed to find a dimm combination that provides %f bytes per channel." % min_ram_per_channel
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slot_dimms = []
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for dimm_slot_index in range(num_dimm_slots_per_channel):
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dimm = available_dimms[best_slot_options[dimm_slot_index]].item
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if dimm.num_gb == 0:
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dimm = None
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slot_dimms.append(dimm)
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return slot_dimms
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def set_ram(self, ram_per_core=None, ram_per_server=None, ram_per_cpu=None):
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# ramUpgradePrice128Gb = {
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# 'c6220':3520.0,
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# 'r620':2010.0,
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# 'r630':1778.0,
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# 'r640':1780.0,
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# 'r730':1778.0,
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# 'r940':960.0, # 32 Gb 2933 MHz RDIMM : 320 €
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# 'c6320':6222.6,
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# 'c4310':1778.0,
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# 'precision3630': 1536.0 }
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cpu = self.cpu
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if ram_per_cpu:
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assert not ram_per_core
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assert not ram_per_server
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if ram_per_core:
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assert not ram_per_server
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assert not ram_per_cpu
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ram_per_cpu = cpu.num_cores * ram_per_core
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if ram_per_server:
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assert not ram_per_core
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assert not ram_per_cpu
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ram_per_cpu = ram_per_server / self.num_cpu_per_server
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ram_per_channel = ram_per_cpu / cpu.num_ram_channels
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slot_dimms = Config._find_dimm_combination(self.configurator.chassis.item.num_dimm_slots_per_channel, ram_per_channel, self.configurator.get_dimm_options())
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# print(cpu.uid, cpu.num_cores, ram_per_channel, [0 if dimm is None else dimm.num_gb for dimm in slot_dimms])
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for cpu_slot_mem in self.cpu_slots_mem:
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for mem_channel in cpu_slot_mem.mem_channels:
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for dimm_slot_index in range(self.configurator.chassis.item.num_dimm_slots_per_channel):
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mem_channel.dimms[dimm_slot_index] = slot_dimms[dimm_slot_index]
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@property
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def ram_size(self):
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ram_size = 0
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for cpu_slot_mem in self.cpu_slots_mem:
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for mem_channel in cpu_slot_mem.mem_channels:
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for dimm_slot_index in range(self.configurator.chassis.item.num_dimm_slots_per_channel):
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dimm = mem_channel.dimms[dimm_slot_index]
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if dimm is not None:
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dimm = self.configurator.get_item(dimm.uid)
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ram_size += self.num_servers * dimm.num_gb
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return ram_size
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@property
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def ram_price(self):
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ram_price = 0.0
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for cpu_slot_mem in self.cpu_slots_mem:
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for mem_channel in cpu_slot_mem.mem_channels:
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for dimm_slot_index in range(self.configurator.chassis.item.num_dimm_slots_per_channel):
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dimm = mem_channel.dimms[dimm_slot_index]
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if dimm is not None:
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dimm_price = self.configurator.get_item_price(dimm.uid)
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ram_price += self.num_servers * dimm_price
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return ram_price
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def get_price(self):
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price = self.configurator.chassis.price
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price += self.num_servers * self.num_cpu_per_server * self.configurator.get_item_price(self.cpu.uid) + self.ram_price
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assert price > 0.0
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return price
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def get_power_consumption(self):
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server_base_power_consumption = 100.0 # rough estimation in watts
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power_consumption = (self.cpu.tdp * self.num_cpu_per_server + server_base_power_consumption) * self.num_servers
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return power_consumption
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def get_flops(self):
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# print('%d servers * %d cpu %s * %d cores @ %f (%d flops/cycle)' % (self.num_servers, self.num_cpu_per_server, str(self.cpu.uid), self.cpu.num_cores, self.cpu.clock, self.cpu.num_dp_flop_per_cycle))
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flops = self.cpu.num_dp_flop_per_cycle * self.cpu.clock * 1.e9 * self.cpu.num_cores * self.num_cpu_per_server * self.num_servers
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return flops
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def _init_dimm_slots(self):
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# create the dimm slots
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self.cpu_slots_mem = []
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if self.cpu is None:
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return
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for cpu_index in range(self.num_cpu_per_server):
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cpu_slot_mem = CpuSlotMem()
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for channel_index in range(self.cpu.num_ram_channels):
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mem_channel = MemChannel()
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for dimm_slot_index in range(self.configurator.chassis.item.num_dimm_slots_per_channel):
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mem_channel.dimms.append(None) # dimm slots are empty
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cpu_slot_mem.mem_channels.append(mem_channel)
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self.cpu_slots_mem.append(cpu_slot_mem)
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def set_cpu(self, cpu):
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self.cpu = cpu
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# update the dimm slots accordingly
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self._init_dimm_slots()
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@property
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def num_cpu_per_server(self):
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return self._num_cpu_per_server
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@num_cpu_per_server.setter
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def num_cpu_per_server(self, num_cpu_per_server):
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self._num_cpu_per_server = num_cpu_per_server
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# update the dimm slots accordingly
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self._init_dimm_slots()
|
|
|
|
@property
|
|
def num_cpus(self):
|
|
return self.num_cpu_per_server * self.num_servers
|
|
|
|
|
|
class Option():
|
|
|
|
def __init__(self, item, price):
|
|
self.item = item
|
|
self.price = price
|
|
|
|
|
|
class Module():
|
|
|
|
def __init__(self, name):
|
|
self.name = name
|
|
self.options = {}
|
|
|
|
def add_option(self, option):
|
|
self.options[option.item.uid] = option
|
|
|
|
|
|
class Configurator():
|
|
|
|
def __init__(self, name):
|
|
self.modules = {}
|
|
|
|
@abstractmethod
|
|
def create_config(self):
|
|
assert False
|
|
|
|
def add_module(self, module):
|
|
self.modules[module.name] = module
|
|
|
|
def get_cpu_options(self):
|
|
return [Cpu(option.item.uid) for option in self.modules['processor'].options.values()]
|
|
|
|
def get_ram_options(self):
|
|
return self.modules['ram'].values()
|
|
|
|
def get_dimm(self, dimm_capacity):
|
|
for dimm_option in self.modules['ram'].options.values():
|
|
dimm = dimm_option.item
|
|
# print(dimm.num_gb)
|
|
if dimm.num_gb == dimm_capacity:
|
|
return dimm
|
|
assert False, 'failed to find an option for a dimm of capacity %d gb' % dimm_capacity
|
|
|
|
def get_dimm_options(self):
|
|
return list(self.modules['ram'].options.values())
|
|
|
|
def get_item(self, item_uid):
|
|
for module in self.modules.values():
|
|
if item_uid in module.options:
|
|
return module.options[item_uid].item
|
|
|
|
def get_item_price(self, item_uid):
|
|
for module in self.modules.values():
|
|
if item_uid in module.options:
|
|
return module.options[item_uid].price
|
|
|
|
|
|
class TableBasedConfigurator(Configurator):
|
|
|
|
def __init__(self, host_type_id, num_cpu_per_server, num_servers=1):
|
|
self.host_type_id = host_type_id
|
|
self.num_cpu_per_server = num_cpu_per_server
|
|
self.num_servers = num_servers
|
|
self.dell_price_table = numpy.genfromtxt('dell_procoptions_table.dat', dtype=("|U15", "|U15", float), names=True, delimiter='\t')
|
|
self.base_config = Config(self)
|
|
self.base_config.num_servers = self.num_servers
|
|
self.base_config.num_cpu_per_server = self.num_cpu_per_server
|
|
|
|
@abstractmethod
|
|
def get_empty_price(self):
|
|
pass
|
|
|
|
@abstractmethod
|
|
def get_dimm_price(self, dimm_capacity):
|
|
pass
|
|
|
|
@abstractmethod
|
|
def get_guarantee_price(self, guarantee_duration):
|
|
pass
|
|
|
|
@abstractmethod
|
|
def get_disk_upgrade_price(self, disk_capacity):
|
|
pass
|
|
|
|
def get_cpu_options(self):
|
|
supported_cpus = []
|
|
for host_type_id, proc_id, proc_option_price in zip(self.dell_price_table['host_type_id'], self.dell_price_table['proc_id'], self.dell_price_table['proc_option_price']):
|
|
if host_type_id == self.host_type_id:
|
|
supported_cpus.append(Cpu(proc_id))
|
|
return supported_cpus
|
|
|
|
|
|
# def create_host_type(host_type_id):
|
|
# if host_type_id == 'c6420':
|
|
# return dell.DellPowerEdgeC6420(host_type_id)
|
|
# if host_type_id == 'c6320':
|
|
# return dell.DellPowerEdgeC6320(host_type_id)
|
|
# if host_type_id == 'c4130':
|
|
# return dell.DellPowerEdgeC4130(host_type_id)
|
|
# if host_type_id == 'r620':
|
|
# return dell.DellPowerEdgeR620(host_type_id)
|
|
# if host_type_id == 'r630':
|
|
# return dell.DellPowerEdgeR630(host_type_id)
|
|
# if host_type_id == 'r640':
|
|
# return dell.DellPowerEdgeR640(host_type_id)
|
|
# if host_type_id == 'r940':
|
|
# return dell.DellPowerEdgeR940(host_type_id)
|
|
# if host_type_id == 'precision3630':
|
|
# return dell.DellPrecision3630(host_type_id)
|
|
# assert False
|
|
|
|
# dom = parse(dell_configurator_html_file_path)
|